Filter
Top Products
System Control Module (SCM)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
12-16 Freescale Semiconductor
At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. If an
instruction fetch access to any of these peripheral modules is attempted, the IPS bus cycle is immediately
terminated with an error.
12.7.3.3 Grouped Peripheral Access Control Registers (GPACR0 & GPACR1)
The on-chip peripheral space starting at IPSBAR is subdivided into sixteen 64-Mbyte regions. Each of the
first two regions has a unique access control register associated with it. The other 14 regions are in reserved
space; the access control registers for these regions are not implemented. Bits [29:26] of the address select
the specific GPACRn to be used for a given reference within the IPS address space. These access control
registers are 8 bits wide so that read, write, and execute attributes may be assigned to the given IPS region.
NOTE
The access control for modules with memory space protected by
PACR0–PACR8 are determined by the PACR0–PACR8 settings. The access
control is not affected by GPACR0, even though the modules are mapped in
its 64-Mbyte address space.
0x027 PACR3 UART2 —
0x028 PACR4 I
2
C QSPI
0x029 PACR5 — —
0x02A PACR6 DTIM0 DTIM1
0x02B PACR7 DTIM2 DTIM3
0x02C PACR8 INTC0 —
1
A value of — in these columns indicates that the bits are not associated with any module and are
reserved.
IPSBAR
Offsets:
0x0030 (GPACR0)
0x0031 (GPACR1)
Access: read/write
76543210
R
LOCK
0 0 0
ACCESS_CTRL
W
Reset:00000000
Figure 12-10. GPACR Register
Table 12-12. Peripheral Access Control Registers (PACRs) (continued)
IPSBAR Offset Name
Modules Controlled
1
ACCESS_CTRL1 ACCESS_CTRL0