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Interrupt Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
14-8 Freescale Semiconductor
NOTE
A spurious interrupt may occur if an interrupt source is being masked in the
interrupt controller mask register (IMR) or a module’s interrupt mask
register while the interrupt mask in the status register (SR[I]) is set to a value
lower than the interrupt’s level. This is because by the time the status
register acknowledges this interrupt, the interrupt has been masked. A
spurious interrupt is generated because the CPU cannot determine the
interrupt source.
To avoid this situation for interrupts sources with levels 1–6, first write a
higher level interrupt mask to the status register, before setting the mask in
the IMR or the module’s interrupt mask register. After the mask is set, return
the interrupt mask in the status register to its previous value. Because level
7 interrupts cannot be disabled in the status register prior to masking, use of
the IMR or module interrupt mask registers to disable level seven interrupts
is not recommended.
14.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)
The INTFRCHn and INTFRCLn registers, each 32 bits, provide a mechanism to allow software generation
of interrupts for each possible source for functional or debug purposes. The system design may reserve one
or more sources to allow software to self-schedule interrupts by forcing one or more of these bits (1 = force
IPSBAR
Offset: 0x0C0C (IMRLn)
Access: Read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
INT_MASK[31:16]
W
Reset1111111111111111
1514131211109876543210
R
INT_MASK[15:1]
MASK
ALL
W
Reset1111111111111111
Figure 14-4. Interrupt Mask Register Low (IMRLn)
Table 14-6. IMRLn Field Descriptions
Field Description
31–1
INT_MASK
Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an
interrupt condition can generate an interrupt. The corresponding IPRLn bit reflects the state of the interrupt signal
even if the corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
0
MASKALL
Mask all interrupts. Setting this bit forces the other 63 bits of the IMRHn and IMRLn to ones, disabling all interrupt
sources, and providing a global mask-all capability.