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Static RAM (SRAM)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
5-4 Freescale Semiconductor
2. Read the source data and write it to the SRAM. Various instructions support this function,
including memory-to-memory move instructions, or the MOVEM opcode. The MOVEM
instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this
opcode generally provides maximum performance.
3. After the data loads into the SRAM, it may be appropriate to load a revised value into the
RAMBAR with a new set of attributes. These attributes consist of the write-protect and address
space mask fields.
The ColdFire processor or an external debugger using the debug module can perform these initialization
functions.
5.3.1 SRAM Initialization Code
The following code segment describes how to initialize the SRAM. The code sets the base address of the
SRAM at 0x2000_0000 and initializes the SRAM to zeros.
RAMBASE EQU 0x20000000 ;set this variable to 0x20000000
RAMVALID EQU 0x00000001
move.l #RAMBASE+RAMVALID,D0 ;load RAMBASE + valid bit into D0.
movec.l D0, RAMBAR ;load RAMBAR and enable SRAM
The following loop initializes the entire SRAM to zero:
lea.l RAMBASE,A0 ;load pointer to SRAM
move.l #8192,D0 ;load loop counter into D0 (SRAM size/4)
SRAM_INIT_LOOP:
clr.l (A0)+ ;clear 4 bytes of SRAM
clr.l (A0)+ ;clear 4 bytes of SRAM
clr.l (A0)+ ;clear 4 bytes of SRAM
clr.l (A0)+ ;clear 4 bytes of SRAM
subq.l #4,D0 ;decrement loop counter
bne.b SRAM_INIT_LOOP ;if done, then exit; else continue looping
5.3.2 Power Management
If the SRAM is used only for data operands, setting the ASn bits associated with instruction fetches can
decrease power dissipation. Additionally, if the SRAM contains only instructions, masking operand
accesses can reduce power dissipation. Table 5-3 shows examples of typical RAMBAR settings.
Table 5-3. Typical RAMBAR Setting Examples
Data Contained in SRAM RAMBAR[7:0]
Instruction Only 0x2B
Data Only 0x35
Instructions and Data 0x21