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Debug Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
28-18 Freescale Semiconductor
28.4.8 Data Breakpoint and Mask Registers (DBR, DBMR)
The data breakpoint register (DBR), specify data patterns used as part of the trigger into debug mode. DBR
bits are masked by setting corresponding DBMR bits, as defined in TDR.
DBR and DBMR are accessible in supervisor mode using the WDEBUG instruction and through the BDM
port using the WDMREG command.
The DBR supports aligned and misaligned references. Table 28-17 shows relationships between processor
address, access size, and location within the 32-bit data bus.
DRc[4:0]: 0x0E (DBR) Access: Supervisor write-only
BDM write-only
313029282726252423222120191817161514131211109876543210
R
WData
Reset––––––––––––––––––––––––––––––––
Figure 28-11. Data Breakpoint Registers (DBR)
Table 28-15. DBR Field Descriptions
Field Description
31–0
Data
Data Breakpoint Value. Contains the value to be compared with the data value from the processor’s local bus as a
breakpoint trigger.
DRc[4:0]: 0x0F (DBMR) Access: Supervisor write-only
BDM write-only
313029282726252423222120191817161514131211109876543210
R
WMask
Reset––––––––––––––––––––––––––––––––
Figure 28-12. Data Breakpoint Mask Registers (DBMR)
Table 28-16. DBMR Field Descriptions
Field Description
31–0
Mask
Data Breakpoint Mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBMR bit allows the
corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a DBMR bit
causes that bit to be ignored.