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Universal Serial Bus, OTG Capable Controller
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
15-14 Freescale Semiconductor
15.4.1.6 OTG Interrupt Control Register (OTG_INT_EN)
The OTG Interrupt Control Register enables the corresponding interrupt status bits defined in the OTG
Interrupt Status Register. Figure 15-12 shows the OTG_INT_EN register.
IPSBAR
Offset:
0x1C_0014 (OTG_INT_EN) Access: User read/write
7 6543210
R
ID_EN
1_MSEC
_EN
LINE_STATE_
EN
Reserved
SESS_VLD
_EN
B_SESS
_EN
Reserved
A_VBUS
_EN
W––
Reset: 0 0 0 X 0 0 X 0
Figure 15-12. OTG Interrupt Control Register
Table 15-16. OTG_INT_EN Field Descriptions
Field Description
7
ID_EN
ID interrupt enable
0 The ID interrupt is disabled
1 The ID interrupt is enabled
6
1_MSEC_EN
1 millisecond interrupt enable
0 The 1msec timer interrupt is disabled
1 The 1msec timer interrupt is enabled
5
LINE_STATE
_EN
Line State change interrupt enable
0 The LINE_STAT_CHG interrupt is disabled
1 The LINE_STAT_CHG interrupt is enabled
4 Reserved.
3
SESS_VLD
_EN
Session valid interrupt enable
0 The SESS_VLD_CHG interrupt is disabled
1 The SESS_VLD_CHG interrupt is enabled
2
B_SESS_EN
B Session END interrupt enable
0 The B_SESS_CHG interrupt is disabled
1 The B_SESS_CHG interrupt is enabled
1 Reserved.
0
A_VBUS_EN
A VBUS Valid interrupt enable
0 The A_VBUS_CHG interrupt is disabled
1 The A_VBUS_CHG interrupt is enabled