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DMA Timers (DTIM0–DTIM3)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-7
22.2.5 DMA Timer Capture Registers (DTCRn)
Each DTCRn latches the corresponding DTCNn value during a capture operation when an edge occurs on
DTINn, as programmed in DTMRn. The internal bus clock is assumed to be the clock source. DTINn
cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation
results if DTINn is set as the clock source when the input capture mode is used.
22.2.6 DMA Timer Counters (DTCNn)
The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Any write to
DTCNn clears it. The timer counter increments on the clock source rising edge (internal bus clock divided
by 1, internal bus clock divided by 16, or DTINn).
IPSBAR
Offset:
0x00_0404 (DTRR0)
0x00_0444 (DTRR1)
0x00_0484 (DTRR2)
0x00_04C4 (DTRR3)
Access: User read/write
313029282726252423222120191817161514131211109876543210
R
REF (32-bit reference value)
W
Reset11111111111111111111111111111111
Figure 22-5. DTRRn Registers
Table 22-5. DTRRn Field Descriptions
Field Description
31–0
REF
Reference value compared with the respective free-running timer counter (DTCNn) as part of the output-compare
function.
IPSBAR
Offset:
0x00_0408 (DTCR0)
0x00_0448 (DTCR1)
0x00_0488 (DTCR2)
0x00_04C8 (DTCR3)
Access: User read-only
313029282726252423222120191817161514131211109876543210
R CAP (32-bit capture counter value)
W
Reset00000000000000000000000000000000
Figure 22-6. DTCRn Registers
Table 22-6. DTCRn Field Descriptions
Field Description
31–0
CAP
Captures the corresponding DTCNn value during a capture operation when an edge occurs on DTINn, as
programmed in DTMRn.