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Universal Serial Bus, OTG Capable Controller
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
15-30 Freescale Semiconductor
5 Reserved
4
EP_CTL_DIS
This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This
applies if and only if the EP_RX_EN and EP_TX_EN bits are also set. SeeTable 15-34
3
EP_RX_EN
This bit, when set, enables the endpoint for RX transfers. SeeTable 15-34
2
EP_TX_EN
This bit, when set, enables the endpoint for TX transfers. SeeTable 15-34
1
EP_STALL
When set this bit indicates that the endpoint is called. This bit has priority over all other control bits in the
EndPoint Enable Register, but it is only valid if EP_TX_EN=1 or EP_RX_EN=1. Any access to this endpoint
causes the USB Module to return a STALL handshake. After an endpoint is stalled it requires intervention from
the Host Controller.
0
EP_HSHK
When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit is
generally set unless the endpoint is Isochronous.
Table 15-34. Endpoint Direction and Control
EPL_CTL_DIS EP_RX_EN EP_TX_EN Endpoint Enable / Direction Control
X 0 0 Disable Endpoint
X 0 1 Enable Endpoint for TX transfers only
X 1 0 Enable Endpoint for RX transfers only
1 1 1 Enable Endpoint for RX and TX transfers
0 1 1 Enable Endpoint for RX and TX as well as control (SETUP) transfers
Table 15-33. BDT_PAGE_03 Field Descriptions (continued)
Field Description