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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
103
9.2.
Description of Each Instruction
<< Start sleep (01 h)
This instruction changes this device into forced sleep, stops the driver/receiver function of 1394 port, and then changed into the status
with this device’s cable cut.
Also, it stops the clock to be input from integrated PLL to IEEE1394 block.
Access to each register is available.
No interrupt this instruction is reported.
Confirm the sleep condition using sleep Bit (Bit4) of flag & status register (address 02h).
<< Remove sleep (02 h)
This instruction releases this device from forced sleep condition.
No interrupt to this instruction is reported.
Confirm the sleep condition release using sleep Bit (Bit4) of flag & status register (address 02h)
<< Asynchronous Receive (03 h)
This instruction reads the out data stored at ASYNC receive specific buffer.
Even though the receive data length does not satisfy with the quadlet unit, this instruction stores up to quadlet unit.
The receive data does not have CRC code and Logical inverse part.
<< Remove busy mode (04 h)
This instruction releases the busy mode set due to receiving normal Asynchronous packet or Self-ID packet addressed to this node.
<<
Send PHY packet (21 h)
This instruction transmits the data stored at ASYNC receive specific buffer.
Do not issue this instruction in case that this instruction is not Bus manager node, or not Isochronous resource manager no de without
existence of Bus manager.
When packet transmit operation is completed normally, this instruction report s the interrupt of “Physical packet send” (INT25).
Store the transmit data at ASYNC transmit specific buffer beforehand.
Logical inverse part is added automatically by this device.