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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
129
(Note)Register and bit necessary for receiving are as follows.
Data
Address
MPEG-TS DSS DV
00h TSPSB=0, CPSB=0
1Ch
TSEN=1,
Set TV1A,TV1B,TV2A,TV2B
according to Ch received and
port.
DSSEN=1,
Set TV1A,TV1B,TV2A,TV2B
according to Ch received and
port.
DVEN=1,
Set TV1A,TV1B,TV2A,TV2B
according to Ch received and
port.
40h Set criteria for Late packet (Ach). -
42h Set criteria for Late packet (Bch). -
3Ch
Ach received : RXSTA=1h, RXCHA(Iso channel No.)
Bch received : RXSTB=1h, RXCHB(Iso channel No.)