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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
44
7.12. Receive DSS Packet Header Indicate Register [A]/Transmit DSS Packet Header
Setting Register [A]
Receive DSS packet header indicate register [A] indicates DSS packet header range of DSS packet received by bridge-Ach.
Transmit DSS packet header setting register [A] sets DSS packet header range of DSS packet received by bridge -Ach.
AD R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R
Rx-SI
F-A
Rx-System clock count-A(high)
1Eh
W
Tx-SIF
-A
Tx-System clock count-A(high)
R Rx-System clock count-A(low)
Rx-E
F-A
Reserved
20h
W Tx-System clock count-A(low)
Tx-E
F-A
reserved
R reserved
22h
W reserved
R reserved
24h
W reserved
R reserved
26h
W reserved
Initial Value “0000 h”
BIT Bit Name Active Value Function
Rx-SIF-A Read - Indicates SIF range of received DSS packet header.
15 (1Eh)
Tx-SIF-A Write - Write in SIF range of transmits DSS packet header.
Rx-System
clock count-A
Read -
Indicate System clock count range of received DSS packet header.
(MSB: 1Eh-bit14 , LSB: 20h-bit8)
14 - 0 (1Eh)
15 - 8(20h)
Tx-System
clock count-A
Write -
Write in System clock count range of transmit DSS packet header.
(MSB: 1Eh-bit14 , LSB: 20h-bit8)
Rx-EF-A Read - Indicates EF range of received DSS packet header.
7(20h)
Tx-EF-A Write - Write in EF range of transmits DSS packet header.
Read - Indicates reserved range of received DSS packet header.
6 - 0(20h)
15 - 0(22h)
15 - 0(24h)
15 - 0(26h)
reserved
Write - Write in reserved range of transmit DSS packet header.