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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
39
7.9. Transmit Offset Setting Register [A]
Transmit offset setting register [A] is the register that sets offset value added to cycle-time-monitor value. Its aim is to generate source
packet header (Time-stamp) added to transmit packet processed by bridge -Ach. (Max. 32 ms)
Time-stamp value is generated on the basis of cycle-time-monitor value at input of first byte of source packet from TSP -IC.
AD R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
14h R/W reserved transmit-offset-A (high)
16h R/W transmit-offset-A (low)
Initial Value “0000 h”
BIT Bit Name Action Value Function
Read - Always indicate ‘0’.
15 - 4 (high) reserved
Write - Always write in ‘0’.
3 - 0 (high)
15 - 12 (low)
Set value to be added to cycle-count range of cycle-time-monitor.
Setting range is 0h to FFh. (unit=125µS).
11 - 0
transmit-offset
-A
Read/
Write
-
Set value to be added to cycle-offset range of cycle-time-monitor.
Setting range is 0h to C00h. (unit=1/24.576 MHz).