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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
105
<< DMA Transmit (Asynchronous) (71h)
This instruction writes in the transmit Asynchronous packet to ASYNC transmit specific buffer using DMA transmit.
Assert DREQ signal after issuing this instruction.
Determine the transmit bite value by transmit data length within packet header, write in up to quadlet unit, then negate DREQ signal.
After completion of writing in, issue the Asynchronous send instruction (31h).
<< DMA Transmit (PHY packet) (72h)
This instruction writes in the transmit PHY packet to ASYNC transmit specific buffer using DMA transfer.
Assert the DREQ signal after issuing this instruction.
Negate the DREQ signal after writing in 2 bites.
After completion of writing in, issue the Send PHY packet instruction (21h).
<< DMA Receive (73h)
This instruction reads out the data stored in ASYNC receive specific FIFO using DMA transfer.
Issue Asynchronous receive instruction (03h) before issuing this instruction.
Assert DREQ signal after issuing this instruction.
Negate DREQ signal when ASYNC receive specific FIFO is empty.