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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
34
7.6. A-buffer Data Port Receive/Transmit
This integrated register is the buffer access port for both ASYNC receive specific buffer and ASYNC transmit specific one.
Read data is able to be read out IEEE1394 packet data in the order received. (MSB: 1
ST
read)
Write data is transmitted as IEEE1394 packet data in the order written in. (MSB: 1
ST
write)
AD R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R ASYNC Receive Specific Buffer Data
0Ch
W ASYNC Transmit Specific Buffer Data
Initial Value Undefined
BIT Bit Name Action Value Function
ASYNC Receive
Specific Buffer
Data
Read -
Read out port of Asynchronous receive specific buffer.
(MSB: bit15, LSB: bit0)
15 - 0
ASYNC Transmit
Specific Buffer
Data
Write -
Write in port of Asynchronous transmit specific buffer.
(MSB: bit15, LSB: bit0)