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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
128
11.6. Isochronous Packet Receiving
The example of control flow for receiving Isochronous packet is shown below.
<Host> <Device>
Figure 11.6 Flow example for transmitting Isochronous packet
END
Set value to registers such as Bridge and
TSPIF(Note).
Set necessary data to registers such as
Bridg and TSPIF.
Receive Late evaluation
Report Receive late occurred(INT30)
interrupt(assert XINT).
Read Receive late occurred (INT30)
interrupt.
Discard source packet.
Receive Late
Yes
No
Transmit source packet to CP LSI.
START
Store source packet in FIFO at Bridge.
Receive Iso packet.
Receive processed source packet from
CP LSI and store it in FIFO at TSPIF.
Output source packet from the TSPIF port
when the value of source packet header
equals to the value of cycle timer.