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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
113
11.1. Initialization
The example of control flow from the system power on to the packet transmitting/receiving possible state is shown below.
In this examle, the device is not operated with cable power supply before turning on the power of system.
<Host> <Device>
Figure 11.1 Example of flow for Initialization
System power ON
Start internal PLL.
Power CPS terminal to ‘L’, up to 500ns.
Power XRESET terminal to ‘L’, up to
400ns.
Receive BUS_RESET
Report Bus reset detected(INT4) interrupt (assert
XINT).
Inner reset and release reset.
Start bus reset process.
END
Read Bus reset detected (INT4)
interrupt.
No
Yes
Report Bus reset complete (INT3)
interrupt (assert XINT).
Read Bus reset complete (INT3)
interrupt.
Complete bus reset process.
Packet
transmitting/receiving
possible
START