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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
25
Chapter 7 Internal Register Function Description
This chapter explains the details of the internal register of MB86617A.
7.1. mode-control Register
7.2. flag & status Register
7.3. instruction fetch Register
7.4. interrupt-factor Indicate Register/interrupt-mask Setting Register
7.5. Receive Acknowledge Indicate Register
7.6. A-buffer Data Port Receive/Transmit
7.7. TSP Transmit Information Setting Register [A]
7.8. TSP Transmit Information Setting Register [B]
7.9. Transmit Offset Setting Register [A]
7.10. Transmit Offset Setting Register [B]
7.11. TSP Receive Information Setting Register
7.12. Transmit DSS Packet Header Setting Register [A]
7.13. Transmit DSS Packet Header Setting Register [B]
7.14. TSP Status Register
7.15. Data Bridge Transmit Information Setting Register 1 [A]
7.16. Data Bridge Transmit Information Setting Register 2 [A]
7.17. Data Bridge Transmit Information Setting Register 3 [B]
7.18. Data Bridge Transmit Information Setting Register 4 [B]
7.19. Data Bridge Receive Information Setting Register
7.20. Transmit Packet Link/Split Setting Register
7.21. Late Packet Decision Range Setting Register [A]
7.22. Late Packet Decision Range Setting Register [B]
7.23. Receive Isochronous Packet Header Indicate Register 1 [A]
7.24. Receive Isochronous Packet Header Indicate Register 2 [A]