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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
59
7.25. Receive Isochronous Packet Header Indicate Register 3 [B]
Receive Isochronous packet header indicate register 3 [B] is the register that indicates Isochronous packet header information received by
bridge-Bch.
AD R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
48h R - - - - - - Rx EMI-B
Rx
o/e-B
Rx SID-B
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “00 b” ‘0’ “00 h”
BIT Bit Name Action Value Function
15 - 9 reserved Read - Always indicate ‘0’.
8 - 7 Rx EMI-B Read -
Indicate EMI range of receive Isochronous packet header.
(MSB: bit8, LSB: bit7)
6 Rx o/e-B Read - Indicates odd/even range of receive Isochronous packet header.
5 - 0 Rx SID-B Read -
Indicate SI range of CIP header of receive Isochronous packet.
(MSB: bit5, LSB: bit0)