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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
104
<< Asynchronous Send (31 h)
This instruction transmits the data stored at the ASYNC transmit specific buffer.
This instruction performs the following serial actions, from access to arbitration by detecting arb-reset-gap, generation and transfer of
packet, to receipt of Acknowledge packet.
When the performances from packet transmit to Acknowledge receive are normally completed, this instruction reports interrupt of
“Asynchronous packet send” (INT17).
In case of occurring an error, it reports interrupt of error, and completes performance.
Store the transmit data at ASYNC transmit specific buffer beforehand.
In case that the transmit data length does not satisfy with the quadlet unit, write in ‘0’ until quadlet unit.
The CRC code is to be added automatically.
Received Acknowledge is indicated at receive Acknowledge indicate register (address 08h).
Note) When destination-ID is set at Broadcast, it is completed without waiting for receipt of Acknowledge.
BIT Operand Name Meaning
7 - 2 Reserved Always specify ‘0’.
1 - 0 Speed code
Specify transmit Speed code . (MSB: 1, LSB: 0)
00 = S100
01 = S200
10 = S400
11 = (reserved)
<< Data-FIFO init (63h)
This instruction clears the contents of buffer specified by Operand.
BIT Operand Name Meaning
7 - 0 FIFO select code
Specify buffer to be cleared. (MSB: 7, LSB: 0)
“11 h” = ASYNC receive specific buffer
“12 h” = ASYNC transmit specific buffer
Other than above = (reserved)