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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
116
<< Flow chart before bus reset completion
<Host> <Device>
Figure 11.2.1.1 Flow example for Self-ID packet receiving before bus reset completion
Start bus reset.
-ID store
END
‘0’
Report Bus reset detected
(INT4)
interrupt. (assert XINT)
(Assert XINT).
Read Bus reset detected (INT4) interrupt.
recv busy bit=0
Store received Self-ID packet to
Asynchronous receive buffer.
Report Bus reset completed (INT3)
(assert XINT) interrupt.
.
Read Bus reset completed (INT3)
interrupt.
recv busy bit=1
Set FIFO according to FIFO mode.
Clear Asynchronous receive buffer.
(Note 1)
‘1’
Bus reset completed.
Yes
No
Bus reset completed .
No
Yes
Report Bus reset completed (INT3)
interrupt.
Read Bus reset completed (INT3)
interrupt.
END