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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
43
Register setting value and selection of output port are shown in the table below.
Bit 15 Bit 14 Bit 7 Bit 6 Bit 1 Bit 0
Receive
Status
TV2B TV1B TV2A TV1A
CMP
SEL
TS
CMP
TSP -IC I/F
Port A
TSP -IC I/F
Port B
0 0 0 1 0 0
Processing-Ach
Receive data
-
0 0 1 0 0 0 -
Processing-Ach
Receive data
0 1 0 0 0 0
Processing-Bch
Receive data
-
1ch receive
1 0 0 0 0 0 -
Processing-Bch
Receive data
1 0 0 1 0 0
Processing-Ach
Receive data
Processing-Bch
Receive data
0 1 1 0 0 0
Processing-Bch
Receive data
Processing-Ach
Receive data
0 0 0 0 0 1
Processing-Ach+Bc
h
Receive data
-
2ch receive
0 0 0 0 1 1 -
Processing-Ach+Bc
h
Receive data