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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
76
7.38. Transmit CGMS/TSCH Indicate Status Register
Transmit CGMS/TSCH indicate status register indicates validity of source packet input from TSP IC I/F.
AD R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
84h R/W - - - - -
act -
TSC
HB
vld-T
SC
HB-2
vld-T
SC
HB-1
- - - - -
act -
TSC
HA
vld-T
SC
HA-2
vld-T
SC
HA-1
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
Read - Always indicate ‘0’.
15 - 11 reserved
Write - Always write in ‘0’.
0
Indicates that the packet indicated in CGMSB-1 and TSCHB-1 (82h-bit7 to 0) was
finally input from port B at TSP IC I/F.
Read
1
Indicates that the packet indicated in CGMSB-2 and TSCHB-2 (82h-bit15 to 8)
was finally input from port B at TSP IC I/F.
10 Act -TSCHB
Write - Clears to ‘0’ by writing “1”.
0
Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h-bit15 to 8) is
invalid.
Read
1
Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h-bit15 to 8) is
valid.
9 Vld-TSCHB-2
Write - Clears to ‘0’ by writing “1”.
0
Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h-bit7 to 0) is
invalid.
Read
1
Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h-bit7 to 0) is
valid.
8 Vld-TSCHB-1
Write - Clears to ‘0’ by writing “1”.
Read - Always indicate ‘0’.
7 - 3 reserved
Write - Always write in ‘0’.