Filter
Top Products
LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
52
7.19. Data Bridge Receive Information Setting Register
Data bridge receive information register performs the setting of receive packet.
AD R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
3Ch R/
Rx
start
-B
Rx
end
-B
Rx channel-B
Rx
start
-A
Rx
end
-A
Rx channel-A
Initial Value ‘0’ ‘0’ “00 h” ‘0’ ‘0’ “00 h”
BIT Bit Name Action Value Function
0
Automatically clears when receive process is executed by bridge-Bch after setting
at ‘1’.
15 Rx start-B
Read/
Write
1 Executes receive process by bridge -Bch.
0
Automatically clears when receive process is stopped by bridge -Bch after setting at
‘1’.
14 Rx end-B
Read/
Write
1 Stops receive process by bridge -Bch.
13~8 Rx channel-B
Read/
Write
-
Write in Isochronous packet channel to be received by bridge-Bch.
(MSB: bit8, LSB: bit3)
0
Automatically clears when receive process is executed by bridge-Ach after setting
at ‘1’.
7 Rx start-A
Read/
Write
1 Starts receive process by bridge -Ach.
0
Automatically clears when receive process is stopped by bridge -Ach after setting at
‘1’.
6 Rx end-A
Read/
Write
1 Stops receive process by bridge -Ach.
5 - 0 Rx-channel-A
Read/
Write
-
Write in Isochronous packet channel to be received by bridge-Ach
(MSB: bit5, LSB: bit0)