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LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
27
7.1. M ode-control Register
Mode-control register is the register that performs the relative setting of various operation mode of this LSI.
AD R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
00h R/W - - - -
CPS
soft
reset
clk
off
s-ID
store
Cp_
trhrou
gh
- - -
Iso-FI
FO no
clr
Asyn-
FIFOs
el
send/re
c
TSP
stand-
by
CP
stand-
by
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’
BIT Bit Name Action Value Function
Read - Always indicate ‘0’.
15 - 12 reserved
Write - Always write in ‘0’.
11 CPS soft reset
Read/
Write
-
PHY/LINK is reset by writing ‘0’ after writing ‘1’ (not automatic clear)
Note:
1) Perform read modify write so as not to re-write other bit.
2) Write ‘0’ after 500 ns minimum passed after writing ‘1’.
0 Not stop clock for providing to TSP I/F, CP I/F and data bridge.
10 clk off
Read/
Write
1
Stop clock for providing to TSP I/F, CP I/F and data bridge when PMODE input
terminal is in ‘H’.
0 Deletes Self-ID packet in spite of receiving it during bus reset.
9
s-ID store
Note 1)
Read/
Write
1
In case of receiving Self-ID packet during bus reset process, this bit stores 512 byte
at maximum accompanying with both Asynchronous receive FIFO and
Asynchronous transmit FIFO.
0 Enable CP -IC interface.(Needs external CP IC)
8 Cp_through
Read/
Write
1 Disable CP -IC interface. CP-IC interface i s internally by passed.
0
TSSYNCA and TSSYNCB signals are neccesary to detect the first byte of the input
data to TSP interface.
7 Sync_in
Read/
Write
1
TSSYNCA and TSSYNCB signals are not neccesary to detect the first byte of the
input data to TSP interface.
0
TSSYNCA and TSSYNCB signals are not asserted when the data is outputted from
TSP interface.
6 Sync_out
Read/
Write
1
TSSYNCA and TSSYNCB signals are asserted when the data is outputted from TSP
interface.
Read 0 Always indicate ‘0’.
5 reserved
Write 0 Always write in ‘0’.
0 Clears receive Isochronous-FIFO when bus reset occurred.
4
Iso-FIFO
no clr
Read/
Write
1 Does not clear Isochronous-FIFO when bus reset occurred.