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DE2-70 User Manual
54
TD1_CLK27 PIN_G15 TV Decoder 1 Clock Input.
TD1_RESET_N PIN_D14 TV Decoder 1 Reset
TD2_D[0] PIN_C10 TV Decoder 2 Data[0]
TD2_D[1] PIN_A9 TV Decoder 2 Data[1]
TD2_D[2] PIN_B9 TV Decoder 2 Data[2]
TD2_D[3] PIN_C9 TV Decoder 2 Data[3]
TD2_D[4] PIN_A8 TV Decoder 2 Data[4]
TD2_D[5] PIN_B8 TV Decoder 2 Data[5]
TD2_D[6] PIN_A7 TV Decoder 2 Data[6]
TD2_D[7] PIN_B7 TV Decoder 2 Data[7]
TD2_HS PIN_E15 TV Decoder 2 H_SYNC
TD2_VS PIN_D15 TV Decoder 2 V_SYNC
TD2_CLK27 PIN_H15 TV Decoder 2 Clock Input.
TD2_RESET_N PIN_B10 TV Decoder 2 Reset
I2C_SCLK PIN_J18 I2C Data
I2C_SDAT PIN_H18 I2C Clock
Table 5.16. TV Decoder pin assignments.
5.13 Implementing a TV Encoder
Although the DE2-70 board does not include a TV encoder chip, the ADV7123 (10-bit high-speed
triple ADCs) can be used to implement a professional-quality TV encoder with the digital
processing part implemented in the Cyclone II FPGA. Figure 5.19 shows a block diagram of a TV
encoder implemented in this manner.
Sync
Gen
SIN
COS
Tables
Y
U
V
Clock
Timing
DSP Block
(Calculate
Composite)
O (Composite)
= Y + U.cos + V.sin
or
or
Y (S-Video)
RCA_Y
DAC
10-bit
C = U.cos + V.sin
(S-Video)
or RCA_Pb
DAC
10-bit
DAC
10-bit
RCA_Pr
DSP Block
S-Video
(Y/C)
10-bit VGA DAC
TV Encoder Block
(Cyclone II 2C70)
Figure 5.19. A TV Encoder that uses the Cyclone II FPGA and the ADV7123.