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DE2-70 User Manual
60
Signal Name FPGA Pin No. Description
DRAM0_A[0] PIN_AA4 SDRAM 1 Address[0]
DRAM0_A[1] PIN_AA5 SDRAM 1 Address[1]
DRAM0_A[2] PIN_AA6 SDRAM 1 Address[2]
DRAM0_A[3] PIN_AB5 SDRAM 1 Address[3]
DRAM0_A[4] PIN_AB7 SDRAM 1 Address[4]
DRAM0_A[5] PIN_AC4 SDRAM 1 Address[5]
DRAM0_A[6] PIN_AC5 SDRAM 1 Address[6]
DRAM0_A[7] PIN_AC6 SDRAM 1 Address[7]
DRAM0_A[8] PIN_AD4 SDRAM 1 Address[8]
DRAM0_A[9] PIN_AC7 SDRAM 1 Address[9]
DRAM0_A[10] PIN_Y8 SDRAM 1 Address[10]
DRAM0_A[11] PIN_AE4 SDRAM 1 Address[11]
DRAM0_A[12] PIN_AF4 SDRAM 1 Address[12]
DRAM_D[0] PIN_AC1 SDRAM 1 Data[0]
DRAM0_D[1] PIN_AC2 SDRAM 1 Data[1]
DRAM_D[2] PIN_AC3 SDRAM 1 Data[2]
DRAM_D[3] PIN_AD1 SDRAM 1 Data[3]
DRAM_D[4] PIN_AD2 SDRAM 1 Data[4]
DRAM_D[5] PIN_AD3 SDRAM 1 Data[5]
DRAM_D[6] PIN_AE1 SDRAM 1 Data[6]
DRAM_D[7] PIN_AE2 SDRAM 1 Data[7]
DRAM_D[8] PIN_AE3 SDRAM 1 Data[8]
DRAM_D[9] PIN_AF1 SDRAM 1 Data[9]
DRAM_D[10] PIN_AF2 SDRAM 1 Data[10]
DRAM_D[11] PIN_AF3 SDRAM 1 Data[11]
DRAM_D[12] PIN_AG2 SDRAM 1 Data[12]
DRAM_D[13] PIN_AG3 SDRAM 1 Data[13]
DRAM_D[14] PIN_AH1 SDRAM 1 Data[14]
DRAM_D[15] PIN_AH2 SDRAM 1 Data[15]
DRAM0_BA_0 PIN_AA9 SDRAM 1 Bank Address[0]
DRAM0_BA_1 PIN_AA10 SDRAM 1 Bank Address[1]
DRAM0_LDQM0 PIN_V9 SDRAM 1 Low-byte Data Mask
DRAM0_UDQM1 PIN_AB6 SDRAM 1 High-byte Data Mask
DRAM0_RAS_N PIN_Y9 SDRAM 1 Row Address Strobe
DRAM0_CAS_N PIN_W10 SDRAM 1 Column Address Strobe