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102 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
LD [%ir]+,%r Load r reg. into location [ir reg.] and increment ir reg. 1 cycle
Function: [ir] ← r, ir ← ir + 1
Loads the content of the r register (A or B) into the data memory addressed by the ir register (X
or Y). Then increments the ir register (X or Y).
Code:
Mnemonic MSB LSB
LD [%X]+,%A 11110111010011EE9H
LD [%X]+,%B 11110111011011EEDH
LD [%Y]+,%A 11110111010111EEBH
LD [%Y]+,%B 11110111011111EEFH
Flags: EICZ
↓ –––
Mode: Src: Register direct
Dst: Register indirect
Extended addressing: Invalid
LD [%ir],imm4 Load immediate data imm4 into location [ir reg.] 1 cycle
Function: [ir] ← imm4
Loads the 4-bit immediate data imm4 into the data memory addressed by the ir register (X or
Y).
Code:
Mnemonic MSB LSB
LD [%X],imm4 111101000i3i2i1i01E80H–1E8FH
LD [%Y],imm4 111101010i3i2i1i01EA0H–1EAFH
Flags: EICZ
↓ –––
Mode: Src: Immediate data
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: LD [%X],imm4 [00imm8] ← imm4 (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
LD [%Y],imm4 [FFimm8] ← imm4 (FFimm8 = FF00H + 00H to FFH)