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44 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
AND %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
AND %B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
AND %F,imm4
AND [%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
AND [%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
OR %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
OR %B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
OR %F,imm4
OR [%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
OR [%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
110100111000X
110100111001X
110100100i3i2i1i0
1101001100000
1101001100001
1101001100010
1101001100011
110100111010X
110100111011X
110100101i3i2i1i0
1101001100100
1101001100101
1101001100110
1101001100111
100001000i3i2i1i0
1101001101000
1101001101100
110100000i3i2i1i0
1101001101001
1101001101101
110100001i3i2i1i0
1101001101010
1101001101110
110100010i3i2i1i0
1101001101011
1101001101111
110100011i3i2i1i0
110110111000X
110110111001X
110110100i3i2i1i0
1101101100000
1101101100001
1101101100010
1101101100011
110110111010X
110110111011X
110110101i3i2i1i0
1101101100100
1101101100101
1101101100110
1101101100111
100001001i3i2i1i0
1101101101000
1101101101100
110110000i3i2i1i0
1101101101001
1101101101101
110110001i3i2i1i0
1101101101010
1101101101110
110110010i3i2i1i0
1101101101011
1101101101111
110110011i3i2i1i0
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓↓↓↓ ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↑↑↑↑ ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
A ← A
∧
A
A ← A
∧
B
A ← A
∧
imm4
A ← A
∧
[X]
A ← A
∧
[X], X ← X+1
A ← A
∧
[Y]
A ← A
∧
[Y], Y ← Y+1
B ← B
∧
A
B ← B
∧
B
B ← B
∧
imm4
B ← B
∧
[X]
B ← B
∧
[X], X ← X+1
B ← B
∧
[Y]
B ← B
∧
[Y], Y ← Y+1
F ← F
∧
imm4
[X] ← [X]
∧
A
[X] ← [X]
∧
B
[X] ← [X]
∧
imm4
[X] ← [X]
∧
A, X ← X+1
[X] ← [X]
∧
B, X ← X+1
[X] ← [X]
∧
imm4, X ← X+1
[Y] ← [Y]
∧
A
[Y] ← [Y]
∧
B
[Y] ← [Y]
∧
imm4
[Y] ← [Y]
∧
A, Y ← Y+1
[Y] ← [Y]
∧
B, Y ← Y+1
[Y] ← [Y]
∧
imm4, Y ← Y+1
A ← A
∨
A
A ← A
∨
B
A ← A
∨
imm4
A ← A
∨
[X]
A ← A
∨
[X], X ← X+1
A ← A
∨
[Y]
A ← A
∨
[Y], Y ← Y+1
B ← B
∨
A
B ← B
∨
B
B ← B
∨
imm4
B ← B
∨
[X]
B ← B
∨
[X], X ← X+1
B ← B
∨
[Y]
B ← B
∨
[Y], Y ← Y+1
F ← F
∨
imm4
[X] ← [X]
∨
A
[X] ← [X]
∨
B
[X] ← [X]
∨
imm4
[X] ← [X]
∨
A, X ← X+1
[X] ← [X]
∨
B, X ← X+1
[X] ← [X]
∨
imm4, X ← X+1
[Y] ← [Y]
∨
A
[Y] ← [Y]
∨
B
[Y] ← [Y]
∨
imm4
[Y] ← [Y]
∨
A, Y ← Y+1
[Y] ← [Y]
∨
B, Y ← Y+1
[Y] ← [Y]
∨
imm4, Y ← Y+1
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode
12
EICZ
11109876543210
↔
ALU logic operation (1/2)
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