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76 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
AND [%ir],%r Logical AND of r reg. and location [ir reg.] 2 cycles
Function: [ir] ← [ir] ∧ r
Performs a logical AND operation of the content of the r register (A or B) and the content of the
data memory addressed by the ir register (X or Y), and stores the result in that address.
Code:
Mnemonic MSB LSB
AND [%X],%A 11010011010001A68H
AND [%X],%B 11010011011001A6CH
AND [%Y],%A 11010011010101A6AH
AND [%Y],%B 11010011011101A6EH
Flags: EICZ
↓ ––↕
Mode: Src: Register direct
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: AND [%X],%r [00imm8] ← [00imm8] ∧ r (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
AND [%Y],%r [FFimm8] ← [FFimm8] ∧ r (FFimm8 = FF00H + 00H to FFH)
AND [%ir]+,%r Logical AND of r reg. and location [ir reg.] and increment ir reg. 2 cycles
Function: [ir] ← [ir] ∧ r, ir ← ir + 1
Performs a logical AND operation of the content of the r register (A or B) and the content of the
data memory addressed by the ir register (X or Y), and stores the result in that address. Then
increments the ir register (X or Y). The flags change due to the operation result of the data
memory and the increment result of the ir register does not affect the flags.
Code:
Mnemonic MSB LSB
AND [%X]+,%A 11010011010011A69H
AND [%X]+,%B 11010011011011A6DH
AND [%Y]+,%A 11010011010111A6BH
AND [%Y]+,%B 11010011011111A6FH
Flags: EICZ
↓ ––↕
Mode: Src: Register direct
Dst: Register indirect
Extended addressing: Invalid