S1C63000 CORE CPU MANUAL EPSON 51
CHAPTER 4: INSTRUCTION SET
INC [%X],n4
[%X]+,n4
[%Y],n4
[%Y]+,n4
[00addr6]
INT imm6
JP %Y
JR %A
%BA
sign8
[00addr6]
JRC sign8
JRNC sign8
JRNZ sign8
JRZ sign8
LD %A,%A
%A,%B
%A,%F
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
%B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
%F,%A
%F,imm4
[%X],%A
[%X],%B
[%X],imm4
[%X],[%Y]
[%X],[%Y]+
[%X]+,%A
[%X]+,%B
[%X]+,imm4
[%X]+,[%Y]
[%X]+,[%Y]+
[%Y],%A
[%Y],%B
[%Y],imm4
[%Y],[%X]
[%Y],[%X]+
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
[%Y]+,[%X]
[%Y]+,[%X]+
LDB %BA,%EXT
%BA,%SP1
%BA,%SP2
%BA,%XH
%BA,%XL
111011000
[ 10H-n4 ]
111011001
[ 10H-n4 ]
111011010
[ 10H-n4 ]
111011011
[ 10H-n4 ]
1000001
a5a4a3a2a1a0
1111110i5i4i3i2i1i0
111111111001X
1111111110001
1111111110000
00000
s7 s6s5 s4s3 s2s1 s0
1111101
a5a4a3a2a1a0
00100
s7 s6s5 s4s3 s2s1 s0
00101
s7 s6s5 s4s3 s2s1 s0
00111
s7 s6s5 s4s3 s2s1 s0
00110
s7 s6s5 s4s3 s2s1 s0
1111011110000
1111011110010
1111111110110
111101100i3i2i1i0
1111011100000
1111011100001
1111011100010
1111011100011
1111011110100
1111011110110
111101101i3i2i1i0
1111011100100
1111011100101
1111011100110
1111011100111
1111111110101
100001011i3i2i1i0
1111011101000
1111011101100
111101000i3i2i1i0
1111011111010
1111011111011
1111011101001
1111011101101
111101001i3i2i1i0
1111011111110
1111011111111
1111011101010
1111011101110
111101010i3i2i1i0
1111011111000
1111011111001
1111011101011
1111011101111
111101011i3i2i1i0
1111011111100
1111011111101
111111101011X
111111100110X
111111100111X
1111111001001
1111111001000
2 ↓ – ●
2 ↓ – ×
2 ↓ – ●
2 ↓ – ×
2 ↓ – ×
3 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ●
2 ↓ ––– ×
1 ↓ ––– ●
1 ↓ ––– ●
1 ↓ ––– ●
1 ↓ ––– ●
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ●
1 ↓ ––– ×
1 ↓ ––– ●
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ●
1 ↓ ––– ×
1 ↓ ––– ●
1 ↓ ––– ×
1 ×
1 ×
1 ↓ ––– ●
1 ↓ ––– ●
1 ↓ ––– ●
2 ↓ ––– ×
2 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
2 ↓ ––– ×
2 ↓ ––– ×
1 ↓ ––– ●
1 ↓ ––– ●
1 ↓ ––– ●
2 ↓ ––– ×
2 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
2 ↓ ––– ×
2 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
[X] ← N's adjust ([X]+1)
[X] ← N's adjust ([X]+1), X ← X+1
[Y] ← N's adjust ([Y]+1)
[Y] ← N's adjust ([Y]+1), Y ← Y+1
[00addr6] ← [00addr6]+1
[SP2-1] ← F, SP2 ← SP2-1
([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← PC+1,
SP1 ← SP1-1, PC ← imm6 (imm6=0100H~013FH)
PC ← Y
PC ← PC+A+1
PC ← PC+BA+1
PC ← PC+sign8+1 (sign8=-128~127)
PC ← PC+[00addr6]+1
If C=1 then PC ← PC+sign8+1 (sign8=-128~127)
If C=0 then PC ← PC+sign8+1 (sign8=-128~127)
If Z=0 then PC ← PC+sign8+1 (sign8=-128~127)
If Z=1 then PC ← PC+sign8+1 (sign8=-128~127)
A ← A
A ← B
A ← F
A ← imm4
A ← [X]
A ← [X], X ← X+1
A ← [Y]
A ← [Y], Y ← Y+1
B ← A
B ← B
B ← imm4
B ← [X]
B ← [X], X ← X+1
B ← [Y]
B ← [Y], Y ← Y+1
F ← A
F ← imm4
[X] ← A
[X] ← B
[X] ← imm4
[X] ← [Y]
[X] ← [Y], Y ← Y+1
[X] ← A, X ← X+1
[X] ← B, X ← X+1
[X] ← imm4, X ← X+1
[X] ← [Y], X ← X+1
[X] ← [Y], X ← X+1, Y ← Y+1
[Y] ← A
[Y] ← B
[Y] ← imm4
[Y] ← [X]
[Y] ← [X], X ← X+1
[Y] ← A, Y ← Y+1
[Y] ← B, Y ← Y+1
[Y] ← imm4, Y ← Y+1
[Y] ← [X], Y ← Y+1
[Y] ← [X], Y ← Y+1, X ← X+1
BA ← EXT
BA ← SP1
BA ← SP2
BA ← XH
BA ← XL
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode
12
EICZ
11109876543210
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