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142 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
XOR [%ir],%r Exclusive OR r reg. and location [ir reg.] 2 cycles
Function: [ir] ← [ir] ∀ r
Performs an exclusive OR operation of the content of the r register (A or B) and the content of
the data memory addressed by the ir register (X or Y), and stores the result in that address.
Code:
Mnemonic MSB LSB
XOR [%X],%A 11011111010001BE8H
XOR [%X],%B 11011111011001BECH
XOR [%Y],%A 11011111010101BEAH
XOR [%Y],%B 11011111011101BEEH
Flags: EICZ
↓ ––↕
Mode: Src: Register direct
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: XOR [%X],%r [00imm8] ← [00imm8] ∀ r (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
XOR [%Y],%r [FFimm8] ← [FFimm8] ∀ r (FFimm8 = FF00H + 00H to FFH)
XOR [%ir]+,%r Exclusive OR r reg. and location [ir reg.] and increment ir reg. 2 cycles
Function: [ir] ← [ir] ∀ r, ir ← ir + 1
Performs an exclusive OR operation of the content of the r register (A or B) and the content of
the data memory addressed by the ir register (X or Y), and stores the result in that address.
Then increments the ir register (X or Y). The flags change due to the operation result of the data
memory and the increment result of the ir register does not affect the flags.
Code:
Mnemonic MSB LSB
XOR [%X]+,%A 11011111010011BE9H
XOR [%X]+,%B 11011111011011BEDH
XOR [%Y]+,%A 11011111010111BEBH
XOR [%Y]+,%B 11011111011111BEFH
Flags: EICZ
↓ ––↕
Mode: Src: Register direct
Dst: Register indirect
Extended addressing: Invalid