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46 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
SLL %A
%B
[%X]
[%X]+
[%Y]
[%Y]+
SRL %A
%B
[%X]
[%X]+
[%Y]
[%Y]+
RL %A
%B
[%X]
[%X]+
[%Y]
[%Y]+
RR %A
%B
[%X]
[%X]+
[%Y]
[%Y]+
1000011110000
1000011110100
1000011100000
1000011100001
1000011100010
1000011100011
1000011110001
1000011110101
1000011100100
1000011100101
1000011100110
1000011100111
1000011110010
1000011110110
1000011101000
1000011101001
1000011101010
1000011101011
1000011110011
1000011110111
1000011101100
1000011101101
1000011101110
1000011101111
1 ↓ – ×
1 ↓ – ×
2 ↓ – ●
2 ↓ – ×
2 ↓ – ●
2 ↓ – ×
1 ↓ – ×
1 ↓ – ×
2 ↓ – ●
2 ↓ – ×
2 ↓ – ●
2 ↓ – ×
1 ↓ – ×
1 ↓ – ×
2 ↓ – ●
2 ↓ – ×
2 ↓ – ●
2 ↓ – ×
1 ↓ – ×
1 ↓ – ×
2 ↓ – ●
2 ↓ – ×
2 ↓ – ●
2 ↓ – ×
A (C←D3←D2←D1←D0←0)
B (C←D3←D2←D1←D0←0)
[X] (C←D3←D2←D1←D0←0)
[X] (C←D3←D2←D1←D0←0), X ← X+1
[Y] (C←D3←D2←D1←D0←0)
[Y] (C←D3←D2←D1←D0←0), Y ← Y+1
A (0→D3→D2→D1→D0→C)
B (0→D3→D2→D1→D0→C)
[X] (0→D3→D2→D1→D0→C)
[X] (0→D3→D2→D1→D0→C), X ← X+1
[Y] (0→D3→D2→D1→D0→C)
[Y] (0→D3→D2→D1→D0→C), Y ← Y+1
A (C←D3←D2←D1←D0←C)
B (C←D3←D2←D1←D0←C)
[X] (C←D3←D2←D1←D0←C)
[X] (C←D3←D2←D1←D0←C), X ← X+1
[Y] (C←D3←D2←D1←D0←C)
[Y] (C←D3←D2←D1←D0←C), Y ← Y+1
A (C→D3→D2→D1→D0→C)
B (C→D3→D2→D1→D0→C)
[X] (C→D3→D2→D1→D0→C)
[X] (C→D3→D2→D1→D0→C), X ← X+1
[Y] (C→D3→D2→D1→D0→C)
[Y] (C→D3→D2→D1→D0→C), Y ← Y+1
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode
12
EICZ
11109876543210
↔
↔
ALU shift and rotate operation
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
131
131
132
132
132
132
133
133
134
134
134
134
120
120
121
121
121
121
122
122
122
123
122
123
LDB %BA,%XL
%BA,%XH
%BA,%YL
%BA,%YH
%BA,%EXT
%BA,%SP1
%BA,%SP2
%BA,imm8
%BA,[%X]+
%BA,[%Y]+
LDB %XL,%BA
%XL,imm8
%XH,%BA
LDB %YL,%BA
%YL,imm8
%YH,%BA
LDB %EXT,%BA
%EXT,imm8
LDB %SP1,%BA
%SP2,%BA
LDB [%X]+,%BA
[%X]+,imm8
LDB [%Y]+,%BA
ADD %X,%BA
%X,sign8
%Y,%BA
%Y,sign8
CMP %X,imm8
%Y,imm8
INC %SP1
%SP2
DEC %SP1
%SP2
1111111001000
1111111001001
1111111001010
1111111001011
111111101011X
111111100110X
111111100111X
01001i7i6i5i4i3i2i1i0
1111111011000
1111111011010
1111111000000
01010i7i6i5i4i3i2i1i0
1111111000001
1111111000010
01011i7i6i5i4i3i2i1i0
1111111000011
111111101010X
01000i7i6i5i4i3i2i1i0
111111100010X
111111100011X
1111111011001
00001i7i6i5i4i3i2i1i0
1111111011011
111111101000X
01100
s7 s6s5 s4s3 s2s1 s0
111111101001X
01101
s7 s6s5 s4s3 s2s1 s0
01110[ FFH - imm8 ]
01111[ FFH - imm8 ]
1111111101000
1111111101100
1111111100000
1111111100100
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
2 ↓ ––– ×
2 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ●
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ●
1 ↓ ––– ×
1 ↑ ––– ×
1 ↑ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
2 ↓ ––– ×
2 ↓ ––– ×
2 ↓ ––– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ – ●
1 ↓ – ●
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
BA ← XL
BA ← XH
BA ← YL
BA ← YH
BA ← EXT
BA ← SP1
BA ← SP2
BA ← imm8
A ← [X], B ← [X+1], X ← X+2
A ← [Y], B ← [Y+1], Y ← Y+2
XL ← BA
XL ← imm8
XH ← BA
YL ← BA
YL ← imm8
YH ← BA
EXT ← BA
EXT ← imm8
SP1 ← BA
SP2 ← BA
[X] ← A, [X+1] ← B, X ← X+2
[X] ← i3~0, [X+1] ← i7~4, X ← X+2
[Y] ← A, [Y+1] ← B, Y ← Y+2
X ← X+BA
X ← X+sign8 (sign8=-128~127)
Y ← Y+BA
Y ← Y+sign8 (sign8=-128~127)
X-imm8 (imm8=0~255)
Y-imm8 (imm8=0~255)
SP1 ← SP1+1
SP2 ← SP2+1
SP1 ← SP1-1
SP2 ← SP2-1
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode
12
EICZ
11109876543210
8/16-bit operation
↔
↔
↔
↔
↔↔↔↔↔↔↔↔
107
107
107
107
106
107
107
105
106
106
110
110
110
110
110
110
109
109
111
111
108
108
108
72
72
72
72
88
88
94
94
90
90