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54 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
SLL [%X]
[%X]+
[%Y]
[%Y]+
SLP
SRL %A
%B
[%X]
[%X]+
[%Y]
[%Y]+
SUB %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
%B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
[%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
[%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
TST [00addr6],imm2
[FFaddr6],imm2
XOR %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
%B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
%F,imm4
[%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
[%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
1000011100000
1000011100001
1000011100010
1000011100011
1111111111101
1000011110001
1000011110101
1000011100100
1000011100101
1000011100110
1000011100111
110000111000X
110000111001X
110000100i3i2i1i0
1100001100000
1100001100001
1100001100010
1100001100011
110000111010X
110000111011X
110000101i3i2i1i0
1100001100100
1100001100101
1100001100110
1100001100111
1100001101000
1100001101100
110000000i3i2i1i0
1100001101001
1100001101101
110000001i3i2i1i0
1100001101010
1100001101110
110000010i3i2i1i0
1100001101011
1100001101111
110000011i3i2i1i0
10010i1i0
a5a4a3a2a1a0
10011i1i0
a5a4a3a2a1a0
110111111000X
110111111001X
110111100i3i2i1i0
1101111100000
1101111100001
1101111100010
1101111100011
110111111010X
110111111011X
110111101i3i2i1i0
1101111100100
1101111100101
1101111100110
1101111100111
100001010i3i2i1i0
1101111101000
1101111101100
110111000i3i2i1i0
1101111101001
1101111101101
110111001i3i2i1i0
1101111101010
1101111101110
110111010i3i2i1i0
1101111101011
1101111101111
110111011i3i2i1i0
2 ↓ – ●
2 ↓ – ×
2 ↓ – ●
2 ↓ – ×
2 ↓ ––– ×
1 ↓ – ×
1 ↓ – ×
2 ↓ – ●
2 ↓ – ×
2 ↓ – ●
2 ↓ – ×
1 ↓ – ↓↑ ×
1 ↓ – ×
1 ↓ – ×
1 ↓ – ●
1 ↓ – ×
1 ↓ – ●
1 ↓ – ×
1 ↓ – ×
1 ↓ – ↓↑ ×
1 ↓ – ×
1 ↓ – ●
1 ↓ – ×
1 ↓ – ●
1 ↓ – ×
2 ↓ – ●
2 ↓ – ●
2 ↓ – ●
2 ↓ – ×
2 ↓ – ×
2 ↓ – ×
2 ↓ – ●
2 ↓ – ●
2 ↓ – ●
2 ↓ – ×
2 ↓ – ×
2 ↓ – ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ ––↑×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ×
1 ↓ ––↑×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
[X] (C←D3←D2←D1←D0←0)
[X] (C←D3←D2←D1←D0←0), X ← X+1
[Y] (C←D3←D2←D1←D0←0)
[Y] (C←D3←D2←D1←D0←0), Y ← Y+1
Sleep
A (0→D3→D2→D1→D0→C)
B (0→D3→D2→D1→D0→C)
[X] (0→D3→D2→D1→D0→C)
[X] (0→D3→D2→D1→D0→C), X ← X+1
[Y] (0→D3→D2→D1→D0→C)
[Y] (0→D3→D2→D1→D0→C), Y ← Y+1
A ← A-A
A ← A-B
A ← A-imm4
A ← A-[X]
A ← A-[X], X ← X+1
A ← A-[Y]
A ← A-[Y], Y ← Y+1
B ← B-A
B ← B-B
B ← B-imm4
B ← B-[X]
B ← B-[X], X ← X+1
B ← B-[Y]
B ← B-[Y], Y ← Y+1
[X] ← [X]-A
[X] ← [X]-B
[X] ← [X]-imm4
[X] ← [X]-A, X ← X+1
[X] ← [X]-B, X ← X+1
[X] ← [X]-imm4, X ← X+1
[Y] ← [Y]-A
[Y] ← [Y]-B
[Y] ← [Y]-imm4
[Y] ← [Y]-A, Y ← Y+1
[Y] ← [Y]-B, Y ← Y+1
[Y] ← [Y]-imm4, Y ← Y+1
[00addr6]
∧
(2
imm2
)
[FFaddr6]
∧
(2
imm2
)
A ← A∀A
A ← A∀B
A ← A∀imm4
A ← A∀[X]
A ← A∀[X], X ← X+1
A ← A∀[Y]
A ← A∀[Y], Y ← Y+1
B ← B∀A
B ← B∀B
B ← B∀imm4
B ← B∀[X]
B ← B∀[X], X ← X+1
B ← B∀[Y]
B ← B∀[Y], Y ← Y+1
F ← F∀imm4
[X] ← [X]∀A
[X] ← [X]∀B
[X] ← [X]∀imm4
[X] ← [X]∀A, X ← X+1
[X] ← [X]∀B, X ← X+1
[X] ← [X]∀imm4, X ← X+1
[Y] ← [Y]∀A
[Y] ← [Y]∀B
[Y] ← [Y]∀imm4
[Y] ← [Y]∀A, Y ← Y+1
[Y] ← [Y]∀B, Y ← Y+1
[Y] ← [Y]∀imm4, Y ← Y+1
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode
12
EICZ
11109876543210
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