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52 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
LDB %BA,%YH
%BA,%YL
%BA,imm8
%BA,[%X]+
%BA,[%Y]+
%EXT,%BA
%EXT,imm8
%SP1,%BA
%SP2,%BA
%XH,%BA
%XL,%BA
%XL,imm8
%YH,%BA
%YL,%BA
%YL,imm8
[%X]+,%BA
[%X]+,imm8
[%Y]+,%BA
NOP
OR %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
%B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
%F,imm4
[%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
[%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
POP %A
%B
%F
%X
%Y
PUSH %A
%B
%F
%X
%Y
RET
RETD imm8
1111111001011
1111111001010
01001i7i6i5i4i3i2i1i0
1111111011000
1111111011010
111111101010X
01000i7i6i5i4i3i2i1i0
111111100010X
111111100011X
1111111000001
1111111000000
01010i7i6i5i4i3i2i1i0
1111111000011
1111111000010
01011i7i6i5i4i3i2i1i0
1111111011001
00001i7i6i5i4i3i2i1i0
1111111011011
111111111111X
110110111000X
110110111001X
110110100i3i2i1i0
1101101100000
1101101100001
1101101100010
1101101100011
110110111010X
110110111011X
110110101i3i2i1i0
1101101100100
1101101100101
1101101100110
1101101100111
100001001i3i2i1i0
1101101101000
1101101101100
110110000i3i2i1i0
1101101101001
1101101101101
110110001i3i2i1i0
1101101101010
1101101101110
110110010i3i2i1i0
1101101101011
1101101101111
110110011i3i2i1i0
1111111101111
1111111101110
1111111101101
1111111101001
111111110101X
1111111100111
1111111100110
1111111100101
1111111100001
111111110001X
11111111110X0
10001i7i6i5i4i3i2i1i0
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
2 ↓ ––– ×
2 ↓ ––– ×
1 ↑ ––– ×
1 ↑ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ●
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ●
2 ↓ ––– ×
2 ↓ ––– ×
2 ↓ ––– ×
1 ↓ ––– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↑↑↑↑ ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
1 ↓ ––– ×
3 ↓ ––– ×
BA ← YH
BA ← YL
BA ← imm8
A ← [X], B ← [X+1], X ← X+2
A ← [Y], B ← [Y+1], Y ← Y+2
EXT ← BA
EXT ← imm8
SP1 ← BA
SP2 ← BA
XH ← BA
XL ← BA
XL ← imm8
YH ← BA
YL ← BA
YL ← imm8
[X] ← A, [X+1] ← B, X ← X+2
[X] ← i3~0, [X+1] ← i7~4, X ← X+2
[Y] ← A, [Y+1] ← B, Y ← Y+2
No operation (PC ← PC+1)
A ← A
∨
A
A ← A
∨
B
A ← A
∨
imm4
A ← A
∨
[X]
A ← A
∨
[X], X ← X+1
A ← A
∨
[Y]
A ← A
∨
[Y], Y ← Y+1
B ← B
∨
A
B ← B
∨
B
B ← B
∨
imm4
B ← B
∨
[X]
B ← B
∨
[X], X ← X+1
B ← B
∨
[Y]
B ← B
∨
[Y], Y ← Y+1
F ← F
∨
imm4
[X] ← [X]
∨
A
[X] ← [X]
∨
B
[X] ← [X]
∨
imm4
[X] ← [X]
∨
A, X ← X+1
[X] ← [X]
∨
B, X ← X+1
[X] ← [X]
∨
imm4, X ← X+1
[Y] ← [Y]
∨
A
[Y] ← [Y]
∨
B
[Y] ← [Y]
∨
imm4
[Y] ← [Y]
∨
A, Y ← Y+1
[Y] ← [Y]
∨
B, Y ← Y+1
[Y] ← [Y]
∨
imm4, Y ← Y+1
A ← [SP2], SP2 ← SP2+1
B ← [SP2], SP2 ← SP2+1
F ← [SP2], SP2 ← SP2+1
X ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1
Y ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1
[SP2-1] ← A, SP2 ← SP2-1
[SP2-1] ← B, SP2 ← SP2-1
[SP2-1] ← F, SP2 ← SP2-1
([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← X, SP1 ← SP1-1
([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← Y, SP1 ← SP1-1
PC ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1
PC ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1
[X] ← i3~0, [X+1] ← i7~4, X ← X+2
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode
12
EICZ
11109876543210
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