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78 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
BIT %r,%r’ Test bit of r reg. with r’ reg. 1 cycle
Function: r ∧ r’
Performs a logical AND of the content of the r’ register (A or B) and the content of the r register
(A or B) to check the bits of the r register. The Z flag is changed due to the operation result, but
the content of the register is not changed.
Code:
Mnemonic MSB LSB
BIT %A,%A 110101111000X1AF0H, (1AF1H)
BIT %A,%B 110101111001X1AF2H, (1AF3H)
BIT %B,%A 110101111010X1AF4H, (1AF5H)
BIT %B,%B 110101111011X1AF6H, (1AF7H)
Flags: EICZ
↓ ––↕
Mode: Src: Register direct
Dst: Register direct
Extended addressing: Invalid
BIT %r,imm4 Test bit of r reg. with immediate data imm4 1 cycle
Function: r ∧ imm4
Performs a logical AND of the 4-bit immediate data imm4 and the content of the r register (A
or B) to check the bits of the r register. The Z flag is changed due to the operation result, but the
content of the register is not changed.
Code:
Mnemonic MSB LSB
BIT %A,imm4 110101100i3i2i1i01AC0H–1ACFH
BIT %B,imm4 110101101i3i2i1i01AD0H–1ADFH
Flags: EICZ
↓ ––↕
Mode: Src: Immediate data
Dst: Register direct
Extended addressing: Invalid