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S1C63000 CORE CPU MANUAL EPSON 143
CHAPTER 4: INSTRUCTION SET
XOR [%ir],imm4 Exclusive OR immediate data imm4 and location [ir reg.] 2 cycles
Function: [ir] ← [ir] ∀ imm4
Performs an exclusive OR operation of the 4-bit immediate data imm4 and the content of the
data memory addressed by the ir register (X or Y), and stores the result in that address.
Code:
Mnemonic MSB LSB
XOR [%X],imm4 110111000i3i2i1i01B80H–1B8FH
XOR [%Y],imm4 110111010i3i2i1i01BA0H–1BAFH
Flags: EICZ
↓ ––↕
Mode: Src: Immediate data
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: XOR [%X],imm4 [00imm8] ← [00imm8] ∀ imm4 (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
XOR [%Y],imm4 [FFimm8] ← [FFimm8] ∀ imm4 (FFimm8 = FF00H + 00H to FFH)
XOR [%ir]+,imm4
Exclusive OR immediate data imm4 and location [ir reg.] and increment ir reg. 2 cycles
Function: [ir] ← [ir] ∀ imm4, ir ← ir + 1
Performs an exclusive OR operation of the 4-bit immediate data imm4 and the content of the
data memory addressed by the ir register (X or Y), and stores the result in that address. Then
increments the ir register (X or Y). The flags change due to the operation result of the data
memory and the increment result of the ir register does not affect the flags.
Code:
Mnemonic MSB LSB
XOR [%X]+,imm4 110111001i3i2i1i01B90H–1B9FH
XOR [%Y]+,imm4 110111011i3i2i1i01BB0H–1BBFH
Flags: EICZ
↓ ––↕
Mode: Src: Immediate data
Dst: Register indirect
Extended addressing: Invalid