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62 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
ADC %r,[%ir] Add with carry location [ir reg.] to r reg. 1 cycle
Function: r ← r + [ir] + C
Adds the content of the data memory addressed by the ir register (X or Y) and carry (C) to the r
register (A or B).
Code:
Mnemonic MSB LSB
ADC %A,[%X] 110011110000019E0H
ADC %A,[%Y] 110011110001019E2H
ADC %B,[%X] 110011110010019E4H
ADC %B,[%Y] 110011110011019E6H
Flags: EICZ
↓ – ↕↕
Mode: Src: Register indirect
Dst: Register direct
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: ADC %r,[%X] r ← r + [00imm8] + C (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
ADC %r,[%Y] r ← r + [FFimm8] + C (FFimm8 = FF00H + 00H to FFH)
ADC %r,[%ir]+ Add with carry location [ir reg.] to r reg. and increment ir reg. 1 cycle
Function: r ← r + [ir] + C, ir ← ir + 1
Adds the content of the data memory addressed by the ir register (X or Y) and carry (C) to the r
register (A or B). Then increments the ir register (X or Y). The flags change due to the operation
result of the r register and the increment result of the ir register does not affect the flags.
Code:
Mnemonic MSB LSB
ADC %A,[%X]+ 110011110000119E1H
ADC %A,[%Y]+ 110011110001119E3H
ADC %B,[%X]+ 110011110010119E5H
ADC %B,[%Y]+ 110011110011119E7H
Flags: EICZ
↓ – ↕↕
Mode: Src: Register indirect
Dst: Register direct
Extended addressing: Invalid