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CHAPTER 3 SPECIFICATIONS
3
3.3 I/O Signals Transferred to/from the CPU Module
3.3.2 Details of input signals
(10)CH Alert occurrence flag (XnC to XnF)
When an alert occurs, the alert definition is stored in CH Alert definition (Un\G5 to Un\G8), and this flag turns
on.
For conditions where this flag turns off, refer to the following.
Page 203, Section 4.12 (6)
The following table lists the particular flag and buffer memory addresses of alert definitions for each channel.
Ex.
Time chart for CH1
Channel
Alert occurrence
flag
ON/OFF status
CH Alert definition (buffer memory
address) ( Page 87, Section 3.4.2 (3))
CH1 XnC
OFF: Alert does not occur.
ON: Alert occurs.
Un\G5
CH2 XnD Un\G6
CH3 XnE Un\G7
CH4 XnF Un\G8
CH1 Alert occurrence flag
(XnC)
OFF
ON
CH1 Alert definition
(Un\G5)
0 Detected alert definition
Executed by the Q64TCN