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1 Hardware Overview 1.2 System Unit Block Diagram
1-10 TECRA M1 Maintenance Manual (960-436)
The system unit is composed of the following major components:
q Processor
• Intel Banias Processor 1.30GHz
– Processor core speed: 1.30GHz (Performance Mode at 1.35V) and 1.20GHz
(Battery Optimized Mode at 0.85V)
– Processor bus speed: 400MHz
– Integrated L1 cache memory: 32KB instruction cache and 32KB write-back data
cache, 4-way set associative
– Integrated L2 cache memory: 1MB ECC protected cache data array, 8-way set
associative
– Integrated NDP
• Intel Banias Processor 1.40GHz
– Processor core speed: 1.40GHz (Performance Mode at 1.35V) and 1.20GHz
(Battery Optimized Mode at 0.85V)
– Processor bus speed: 400MHz
– Integrated L1 cache memory: 32KB instruction cache and 32KB write-back data
cache, 4-way set associative
– Integrated L2 cache memory: 1MB ECC protected cache data array, 8-way set
associative
– Integrated NDP
• Intel Banias Processor 1.50GHz
– Processor core speed: 1.50GHz (Performance Mode at 1.35V) and 1.20GHz
(Battery Optimized Mode at 0.85V)
– Processor bus speed: 400MHz
– Integrated L1 cache memory: 32KB instruction cache and 32KB write-back data
cache, 4-way set associative
– Integrated L2 cache memory: 1MB ECC protected cache data array, 8-way set
associative
– Integrated NDP
• Intel Banias Processor 1.60GHz
– Processor core speed: 1.60GHz (Performance Mode at 1.35V) and 1.20GHz
(Battery Optimized Mode at 0.85V)
– Processor bus speed: 400MHz
– Integrated L1 cache memory: 32KB instruction cache and 32KB write-back data
cache, 4-way set associative