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General Purpose I/O Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 13-3
Table 13-1. Registers in the MCF52211 Ports Address Space
Address
1
1
The register address is the sum of the IPSBAR address and the value in this column.
31–24 23–16 15–8 7–0
Access
2
2
S/U = supervisor or user mode access. User mode accesses to supervisor-only addresses have no effect and cause a
cycle termination transfer error.
Port Output Data Registers
0x10_0000 Reserved
0x10_0004 Reserved
0x10_0008 PORTNQ Reserved PORTAN PORTAS S/U
0x10_000C PORTQS Reserved PORTTA PORTTC S/U
0x10_0010 PORTTD PORTUA PORTUB PORTUC S/U
0x10_0014 PORTDD Reserved Reserved Reserved S/U
Port Data Direction Registers
0x10_0018 Reserved
0x10_001C Reserved
0x10_0020 DDRNQ Reserved DDRAN DDRAS S/U
0x10_0024 DDRQS Reserved DDRTA DDRTC S/U
0x10_0028 DDRTD DDRUA DDRUB DDRUC S/U
0x10_002C DDRDD Reserved Reserved Reserved S/U
Port Pin Data/Set Data Registers
0x10_0030 Reserved
0x10_0034 Reserved
0x10_0038 PORTNQP/SETNQ Reserved PORTANP/SETAN PORTASP/SETAS S/U
0x10_003C PORTQSP/SETQS Reserved PORTTAP/SETTA PORTTCP/SETTC S/U
0x10_0040 PORTTDP/SETTD PORTUAP/SETUA PORTUBP/SETUB PORTUCP/SETUC S/U
0x10_0044 PORTDDP/SETDD Reserved Reserved Reserved S/U
Port Clear Output Data Registers
0x10_0048 Reserved
0x10_004C Reserved
0x10_0050 CLRNQ Reserved CLRAN CLRAS S/U
0x10_0054 CLRQS Reserved CLRTA CLRTC S/U
0x10_0058 CLRTD CLRUA CLRUB CLRUC S/U
0x10_005C CLRDD Reserved Reserved Reserved S/U
Port Pin Assignment Registers
0x10_0060 Reserved
0x10_0064 Reserved
0x10_0068 PNQPAR PANPAR PASPAR S/U
0x10_006C PQSPAR PTAPAR PTCPAR S/U
0x10_0070 PTDPAR PUAPAR PUBPAR PUCPAR S/U
0x10_0074 PDDPAR Reserved Reserved Reserved S/U
Port Pad Control Registers
0x10_0078 PSRR[31:0] S/U
0x10_007C PDSR[31:0] S/U