Freescale Semiconductor MCF52212 Network Card User Manual


 
UART Modules
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
24-2 Freescale Semiconductor
NOTE
The DTINn pin can clock UARTn. However, if the timers are used, input
capture mode is not available for that timer.
The serial communication channel provides a full-duplex asynchronous/synchronous receiver and
transmitter deriving an operating frequency from the internal bus clock or an external clock using the timer
pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start,
stop, and parity bits. It outputs the resulting stream on the transmitter serial data output (UTXDn). See
Section 24.4.2.1, “Transmitter.”
The receiver converts serial data from the receiver serial data input (URXDn) to parallel format, checks
for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the bus
during read operations. The receiver may be polled, interrupt driven, or use DMA requests for servicing.
See Section 24.4.2.2, “Receiver.”
NOTE
The GPIO module must be configured to enable the peripheral function of
the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”)
prior to configuring the UART module.
24.1.2 Features
The device contains three independent UART modules with:
Each clocked by external clock or internal bus clock (eliminates need for an external UART clock)
Full-duplex asynchronous/synchronous receiver/transmitter
Quadruple-buffered receiver
Double-buffered transmitter
Independently programmable receiver and transmitter clock sources
Programmable data format:
5–8 data bits plus parity
Odd, even, no parity, or force parity
One, one-and-a-half, or two stop bits
Each serial channel programmable to normal (full-duplex), automatic echo, local loopback, or
remote loopback mode
Automatic wake-up mode for multidrop applications
Four maskable interrupt conditions
All three UARTs have DMA request capability
Parity, framing, and overrun error detection
False-start bit detection
Line-break detection and generation
Detection of breaks originating in the middle of a character
Start/end break interrupt/status