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Universal Serial Bus, OTG Capable Controller
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-29
15.4.1.22 Endpoint Control Registers 0 – 15 (ENDPT0–15)
The Endpoint Control Registers contain the endpoint control bits for each of the 16 endpoints available
within the USB Module for a decoded address. The format for these registers is shown in the following
figure. Endpoint 0 (ENDPT0) is associated with control pipe 0 which is required for all USB functions.
Therefore, after a USB_RST interrupt occurs the ColdFire core should set the ENDPT0 register to contain
0x0D.
In Host mode ENDPT0 is used to determine the handshake, retry and low speed characteristics of the host
transfer. For Host mode control, bulk and interrupt transfers the EP_HSHK bit should be set to 1. Fort
Isochronous transfers it should be set to 0. Common values to use for ENDPT0 in host mode are 0x4D for
Control, Bulk, and Interrupt transfers, and 0x4C for Isochronous transfers.
Figure 15-29 shows the BDT Page Register 3.
IPSBAR
Offsets:
0x1C_00C0 (ENDPT0)
0x1C_00C4 (ENDPT1)
0x1C_00C8 (ENDPT2)
0x1C_00CC (ENDPT3)
0x1C_00D0 (ENDPT4)
0x1C_00D4 (ENDPT5)
0x1C_00D8 (ENDPT6)
0x1C_00DC (ENDPT7)
0x1C_00E0 (ENDPT8)
0x1C_00E4 (ENDPT9)
0x1C_00E8 (ENDPT10)
0x1C_00EC (ENDPT11)
0x1C_00F0 (ENDPT12)
0x1C_00F4 (ENDPT13)
0x1C_00F8 (ENDPT14)
0x1C_00FC (ENDPT15)
Access: User read/write
76543210
R
HOST_WO
_HUB
RETRY_DIS
0
EP_CTL
_DIS
EP_RX
_EN
EP_TX
_EN
EP_STALL EP_HSHK
W
Reset:00000000
Figure 15-29. BDT_PAGE_03 Register
Table 15-33. BDT_PAGE_03 Field Descriptions
Field Description
7
HOST_WO
_HUB
This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0). When set this
bit allows the host to communicate to a directly connected low speed device. When cleared, the host produces
the PRE_PID then switch to low speed signaling when sending a token to a low speed device as required to
communicate with a low speed device through a hub.
6
RETRY_DIS
This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0). When set this
bit causes the host to not retry NAK’ed (Negative Acknowledgement) transactions. When a transaction is
NAKed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When this bit is
cleared NAKed transactions is retried in hardware. This bit must be set when the host is attempting to poll an
interrupt endpoint.