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Chapter 1
Overview
CPUs and Memories
41
CPUs and Memories
The cell provides the processing and memory resources required by each sx2000 system configuration. Each
cell is comprises the following components: four processor module sockets, a single cell (or coherency)
controller ASIC, a high-speed crossbar interface, a high-speed I/O interface, eight memory controller ASICs,
capacity for up to 32 double-data rate (DDR) DIMMs, high-speed clock distribution circuitry, a management
subsystem interface, scan (JTAG) circuitry for manufacturing test, and a low-voltage DC power interface.
Figure 1-8 shows the locations of the major components.
Figure 1-8 Cell Board
Cell Controller
The heart of the cell design is the cell controller (CC). The CC provides two front side bus (FSB) interfaces,
with each FSB connected to two processor modules. The communication bandwidth, 6.8 GBs sustained at
266.67 MH, on each FSB. this bandwidth is shared by the two processor modules on the FSB. Interfaces
external to the cell provided by the CC consist of three crossbar links, referred to as the fabric interface, and a
remote I/O subsystem link. The fabric interface enables multiple cells to communicate with each other across
a self-correcting, high-speed communication pathway. Sustained crossbar bandwidth is 8.5 GBs per link at 3.0
GT/s, or 25.5 GBs across the three links.
CPUs
CC
Memory
Power