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Chapter 1
Overview
CPUs and Memories
47
Platform Dependant Hardware
The platform dependent hardware's (PDH) includes functionality that is required by both system and
management firmware. Features provided by the PDH provide the following features:
- An interface that is capable of passing multiple forms of information between system firmware and the
management processor (MP, on the SBC) by the platform dependant hardware controller (PDHC, on the PDH
daughter card)
- Flash EPROM for PDHC boot code storage.
- PDHC SRAM for operational instruction and data storage
- System management bus (SMBus) for reading the processor module's information EEPROM, scratch
EEPROM, and thermal sensing device
- I2C Bus for reading PDH, cell, and cell power board FRU ID information
- Serial presence detect (SPD) bus for detection and investigation of loaded DIMMs
- PDH resources accessible by the processors (system firmware) and the management subsystem.
- Flash EPROM for system firmware boot-strap code storage and update capability.
- Battery-backed NVRAM and real time clock (RTC) chip to provide wall-clock time
- Memory-mapped registers for configuration related information
Reset
The sequencing and timing of reset signals is controlled by the LPM, a field-programmable gate array (FPGA)
that resides on the cell. The LPM is powered by the housekeeping rail and has a clock input from the PDH
daughter card that runs continuously at 8 MHz. This enables the LPM and the rest of the utility subsystem
interface to operate regardless of the power state of the cell.
Cell reset can be initiated from multiple sources:
- Power enable of the Cell (initial power-on)
- Backplane Reset will cause installed cells to reset or cell reset initiated from PDHC in direct response to an
MP command or during a system firmware update
- System firmware-controlled "soft" reset initiated by writing into the Dillon Test and Reset register
Cell OL*
For an online add (OLA) of a cell, the CC goes through the normal power-on reset sequence.
For an online delete (OLD) of a cell, software does clean up to the I/O (SBA) interface to put it in reset mode
and hold it there. When the I/O (SBA) link is held in reset, the cell is ready for power to be turned off and the
cell to be removed.