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Chapter 1
Overview
CPUs and Memories
42
The remote I/O link provides a self-correcting, high-speed communication pathway between the cell and the
I/O subsystem through a pair of cables. Sustained I/O bandwidth is 5.5 GBs for a 50 percent inbound and
outbound mix, and roughly 4.2 GBs for a range of mixes. The CC interfaces to the cell's memory system. The
memory interface is capable of providing a sustained bandwidth of 14 to 16 GBs at 266.67 MH to the cell
controller.
Processor Interface
The CC has two separate FSB interfaces, and each of those FSB is connected to two processor sockets in a
standard three-drop FSB configuration. The CC FSB interface is pinned out exactly like that of its
predecessor CC, in order to preserve past cell routing. The CC pin out was specifically designed to minimize
total routing delay without sacrificing timing skew between the FSB address and data and control signals.
Such tight routing controls allow the FSB to achieve a frequency of 266.67 MH, and the data to be
transmitted on both edges of the interface clock. With the 128-bit Front Side Bus capable of achieving 533.33
MT/s, the desired 8.5 GBs burst data transfer rate can be realized.
Processors
There are several processor families supported and the processors are already installed on the cell board. All
processors require that a minimum firmware version be installed. See Table 1-2 for the processors supported.
Rules for Processor Mixing
• Processor families can not be mixed on a cell board or within a partition
• Processor frequencies can not be mixed on a cell board or within a partition
• Cache sizes can not be mixed on a cell board or within a partition
• Major processor steppings can not be mixed on a cell board or within a partition
Cell Memory System
Each cell in the sx2000 system has its own independent memory system. This memory subsystem consists of
four logical memory subsystems that achieve a combined bandwidth of 17 GBs peak, 14-16 GBs sustained.
This cell design is the first of the Superdome designs to support the use of DDR I/O DRAM. These DIMMs are
to be based on DDR-II protocol, and the cell design supports DIMM capacities of 1, 2, 4 or 8 GBytes using
monolithic DRAMs. Non-monolithic, or stacked, DRAMS are not supported on the sx2000, as the additional
capacitive load, and/or requirement for additional chip selects is not accommodated by the new chipset. All
DIMMs used in the sx2000 are compatible with those used in other new CEC platforms, although other
Table 1-2 Supported Processors and Minimum Firmware Version Required
Processor Family
Minimum Firmware
Version or Later
Core
Frequency
Itanium
2 single-core processors with 9 MB cache 4.3e (IPF SFW 004.080.000) 1.6 GHz
Itanium
2 dual-core processors with 18 MB cache 5.5d (IPF SFW 005.024.000) 1.6 GHz
Itanium
2 dual-core processors with 24 MB cache 5.5d (IPF SFW 005.024.000) 1.6 GHz