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Chapter 1
Overview
CPUs and Memories
44
industry-standard DIMM. This increase in height allows the DIMM to accommodate twice as many DRAMs
as an industry-standard DIMM and to provide redundant address and control signal contacts not available on
industry-standard DDR2 DIMMs.
Memory Interconnect
MID bus data is transmitted via the four 72-bit, ECC-protected MID buses, each with a clock frequency equal
to the CC s core frequency. The data is transmitted on both edges of the clock, so the data transfer rate (533
MT/s) of each MID is twice the MID clock frequency (267 MHz). A configuration of at least eight DIMMs (two
in each quadrant) activates all four MID buses, and the theoretical bandwidth of the memory subsystem can
be calculated as follows: (533 MT/s * 8 Bytes/T * 4) = 17 GBs The MID buses are bit-sliced across two memory
controllers with 36-bits of data going to each memory controller. Each memory controller, in turn, takes that
high-speed data (533 MT/s) from the MID, and combines four consecutive MID transfers to form one 144-bit
DRAM bus. This DRAM bus is routed out in two 72-bit buses to two DIMM sets, which comprise four DIMMs
each. The DDR DRAM bus runs at 267 MT/s, and data is clocked on both edges of the clock.
The DDR DRAM address and control (MIA) signals for each quadrant originate at the CC and are routed to
the DIMMs through the memory controller. On previous systems, these signals did not touch the memory
chips. Instead they were routed to the DIMMs through fan-out buffers. The DRAM address and control
signals are protected by parity so that signaling errors are detected, and do not cause silent data corruption.
The MIA bus, comprised of the SDRAM address and control signals, is checked for parity by the memory
controller. Each of the thirty-two DIMMs can generating a unique parity error signal that is routed to one of
four parity error inputs per memory controller. Each memory controller then logically gates the DIMM parity
error signals it receives with its own internal parity checks for the MIC and MIT buses. This logical gating
results in a single parity error output that is driven to the CC and latched as an event in an internal
memory-mapped register.
Eight unique buses of command and control signals are transmitted from the CC to each memory controller
simultaneously with the appropriate MID bus interconnect. Each memory interface control (MIC) bus
comprises four signals running at 533 MT/s. Each command on the MIC bus takes four cycles to transmit, and
is protected by parity so that signaling errors are detected and not cause silent data corruption.
Four memory interface tag (MIT) buses are routed between the CC and the designated tag memory
controllers. MIT buses run at 533 MT/s and use the same link type as the MID buses. Each MIT bus
comprises six signals and a differential strobe pair for de-skewing. As with the MIA and MIC buses, the MIT
is protected by parity so that signaling errors will be detected and thus not cause silent data corruption.
Mixing DIMMs of Different sizes
Mixing of different sized DIMMs is allowed, provided the following rules are obeyed:
- An echelon of DIMMs consists of two DIMMs of the same type.
- All supported DIMM sizes may be present on a single cell board at the same time, provided previous rule is
satisfied.
- Memory must be added in increments of one echelon.
- The amount of memory contained in an interleaved group must be 2n bytes.
Memory Interleaving
Memory is interleaved in the following ways on the new sx2000 systems:
- MBAT (across DIMMs)