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Chapter 1
Overview
I/O Subsystem
50
PCI Slots
For maximum performance and availability, each PCI slot is sourced by its own LBA chip and is supported by
its own portion of a hot-plug controller. All slots are designed to Revision 2.2 of the PCI specification and
Revision 2.0a of the PCI-X specification and can support full size. Shorter and smaller cards are supported, as
are 32-bit cards.
Slot 0 support for the core I/O card has been removed on the SIOBP. The core I/O provided a base set of I/O
functions required by Superdome protection domains. In past Superdomes, PCI slot 0 of the I/O backplane
provided a secondary edge connector to support a core I/O card. In the sx2000 chipset, the core I/O function
has been moved onto the PDH card so the extra core I/O sideband connector has been removed from the
SIOBP board.
The SIOBPs ten outermost slots support only 3.3 V signaling (PCI or PCI-X Mode 1). The two innermost slots
support either 3.3 V or 1.5 V (PCI-X Mode 2) signaling. All SIOBP PCI connectors physically prevent 5 V
signaling cards from being installed.
PCI Hot Swap Support
Associated with each pair of PCI slots is a dual-slot hot-swap controller IC plus an assortment of power FETs,
indicator LEDs, and other discrete components. These components enable the online addition, replacement,
and deletion of individual PCI cards without disturbing the operation of other cards in the system. LBAs
provide the control/status signals and internal registers necessary for firmware to control and monitor the
power status of a PCI slot. LBAs also provide firmware control of the attention LED. The slot state LEDs are
driven directly by the hot swap controller IC.
I/O Backplane System Connections
The connector used for system interconnects to and from the I/O backplane is a modular 2mm hard metric
connector with modules for the HSS link, clocks, and various control signals. In order to support both the
12-slot and the future 6-slot variations of the I/O backplane, four groups of connector modules are provided on
the master I/O backplane for the 24 possible PCI slots, with HSS link, clock, and control connections available
in each group. Even though the width of the SIOBP 12-slot backplane causes it to span two connector groups,
it connects only to the signals in one of these groups. Each connector module group is made up of two
connectors.
I/O Backplane Power
48 V and 5 V housekeeping for the I/O chassis is brought into the I/O power board from cable assemblies that
are supported directly by the sheet metal of the I/O system sub-frame in the cabinet. On the I/O Power board,
the 48V is converted to +1.5, +3.3, +5, +12, and –12, and brought up through the I/O power transfer board.
+5V housekeeping is also brought up, for the SIOBP FPGA, FRU ID Serial EEPROM, and for the chassis ID
buffers.
Power Sequencing
Both the SBA and LBA (Mercury) devices have requirements regarding the order in which the power rails are
brought up. This function is performed by the SIOBP FPGA (formerly called the LPM FPGA when it was on
the SIOPB). The power-on sequence is as follows: 1. +12 V, -12 V 2. +5 V 3. +1.5 V 4. +3.3 V and +2.5 V