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I
2
C Controller
The I
2
C controller base address is D000h and shares INT2 with the SPI controller. The I
2
C bus
interface requires two bi-directional buffers with open collector (or open drain) outputs and
Schmitt inputs.
Operating Modes
The following sections describe the possible I
2
C operating modes:
Master Transmit Mode, page 13
Master Receive Mode, page 16
Slave Transmit Mode, page 19
Slave Receive Mode, page 20
Master Transmit Mode
In master transmit mode, the I
2
C controller transmits a number of bytes to a slave receiver.
To enter the master transmit mode, set the STA bit to one. The following actions occur:
1. The DATA register loads either a 7-bit slave address or the first part of a 10-bit slave
address, with the least-significant bits cleared to zero, to specify transmit mode.
2. The M I
2
C tests the I
2
C bus and sends a START condition when the bus is free.
3. The IFLG bit is set and the status code in the Status register becomes 08h.
4. The IFLG bit clears to zero to prompt the transfer to continue.
5. After the 7-bit slave address (or the first part of a 10-bit address) and the write bit are sent,
the IFLG is set again.
During this sequence, a number of status codes are possible in the Status register (see Table
3-1).
Note: In 10-bit addressing, after the first part of a 10-bit address and the write bit transmit
successfully, the status code is 18h or 20h.