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Table 5-34. Tx/Rx Message Level Register ..............................................................................71
Table 5-35. Tx/Rx Message Level Register Definitions.............................................................71
Table 5-36. Interrupt Flags........................................................................................................72
Table 5-37. Interrupt Flag Definitions........................................................................................72
Table 5-38. Interrupt Enable Registers .....................................................................................73
Table 5-39. Interrupt Enable Register Definitions......................................................................73
Table 5-40. Interrupt Enable Registers .....................................................................................74
Table 5-41. Interrupt Enable Register Definitions......................................................................74
Table 5-42. Bit Rate Divisor Register........................................................................................75
Table 5-43. Bit Rate Divisor Register Definitions ......................................................................75
Table 5-44. Configuration Register ...........................................................................................76
Table 5-45. Configuration Register Definitions..........................................................................76
Table 5-46. Acceptance Filter Enable Register.........................................................................78
Table 5-47. Acceptance Filter Enable Register Definitions .......................................................78
Table 5-48. Acceptance Mask 0 Register .................................................................................78
Table 5-49. Acceptance Mask 0 Register Definitions................................................................78
Table 5-50. Acceptance Mask Register: ID 12..........................................................................79
Table 5-51. Acceptance Mask Register: ID12 Definitions ......................................................... 79
Table 5-52. Acceptance Mask Register: Data 55......................................................................79
Table 5-53. Acceptance Mask Register: Data 55 Definitions .................................................... 79
Table 5-54. Acceptance Code Register ....................................................................................80
Table 5-55. Acceptance Code Register Definitions...................................................................80
Table 5-56. Acceptance Mask Register: ID12...........................................................................80
Table 5-57. Acceptance Mask Register: ID12 Definitions ......................................................... 80
Table 5-58. Acceptance Mask Register: Data 55......................................................................80
Table 5-59. Acceptance Mask Register: Data 55 Definitions .................................................... 80
Table 5-60. Arbitration Lost Capture Register...........................................................................81
Table 5-61. Arbitration Lost Capture Register Definitions .........................................................81
Table 5-62. Error Capture Register...........................................................................................82
Table 5-63. Error Capture Register Definitions .........................................................................82
Table 5-64. Frame Reference Register..................................................................................... 83
Table 5-65. Error Capture Register Definitions .........................................................................83
List of Figures
Figure 3-1. DSTni I
2
C Controller Block Diagram .......................................................................12
Figure 4-1. Buffer Descriptor Table...........................................................................................33
Figure 4-2. USB Token Transaction..........................................................................................37
Figure 3. Enable Host Mode and Configure a Target Device....................................................51
Figure 4. Full-Speed Bulk Data Transfers to a Target Device................................................... 52
Figure 4-5. Pull-up/Pull-down USB............................................................................................53
Figure 5-1. TX Message Routing ..............................................................................................63
Figure 5-2. RX Message Routing..............................................................................................66
Figure 5-3. CAN Operating Mode.............................................................................................. 75
Figure 5-4. Bit Time, Time Quanta, and Sample Point Relationships .......................................77
Figure 5-5. CAN Bus Interface..................................................................................................84
Figure 5-6. CAN Connector.......................................................................................................84
Figure 5-7. Power for CAN........................................................................................................85
Figure 5-8. CAN Transceiver and Isolation Circuits ..................................................................86