Xilinx UG492 Switch User Manual


 
Ethernet AVB Endpoint User Guide www.xilinx.com 129
UG492 July 23, 2010
Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC
PARAMETER C_MEM0_HIGHADDR = 0xcc00ffff
BUS_INTERFACE SPLB = mb_plb
PORT reset = sys_periph_reset
# Connect as per Figure 12-9
PORT tx_clk = Temac0AvbTxClk
PORT tx_clk_en = Temac0AvbTxClkEn
PORT rx_clk = Temac0AvbRxClk
PORT rx_clk_en = Temac0AvbRxClkEn
PORT tx_data = Avb2Mac0TxData
PORT tx_data_valid = Avb2Mac0TxDataValid
PORT tx_underrun = Avb2Mac0TxUnderrun
PORT tx_ack = Mac02AvbTxAck
PORT rx_data = Mac02AvbRxData
PORT rx_data_valid = Mac02AvbRxDataValid
PORT rx_frame_good = Mac02AvbRxFrameGood
PORT rx_frame_bad = Mac02AvbRxFrameBad
PORT legacy_tx_data = Temac02AvbTxData
PORT legacy_tx_data_valid = Temac02AvbTxDataValid
PORT legacy_tx_underrun = Temac02AvbTxUnderrun
PORT legacy_tx_ack = Avb2Temac0TxAck
PORT legacy_rx_data = Avb2Temac0RxData
PORT legacy_rx_data_valid = Avb2Temac0RxDataValid
PORT legacy_rx_frame_good = Avb2Temac0RxFrameGood
PORT legacy_rx_frame_bad = Avb2Temac0RxFrameBad
PORT rtc_clk = Temac0AvbTxClk
# Unused in this example: connect to custom pcores
PORT av_tx_data = net_gnd
PORT av_tx_valid = net_gnd
PORT av_tx_done = net_gnd
# PORT av_tx_ack =
# PORT av_rx_data =
# PORT av_rx_valid =
# PORT av_rx_frame_good =
# PORT av_rx_frame_bad =
# PORT rtc_nanosec_field =
# PORT rtc_sec_field =
# PORT clk8k =
# PORT rtc_nanosec_field_1722 =
# PORT interrupt_ptp_tx =
# Connected Interrupts (to a xps_intc core)
PORT interrupt_ptp_timer = AvbPtpInt
PORT interrupt_ptp_rx = AvbRxInt
END