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Ethernet AVB Endpoint User Guide www.xilinx.com 151
UG492 July 23, 2010
Implementation Scripts
Implementation Scripts
The implementation script is either a shell script or batch file that processes the example
design through the Xilinx tool flow and is one of the following locations:
Linux
<project_dir>/<component_name>/implement/implement.sh
Windows
<project_dir>/<component_name>/implement/implement.bat
The implement script performs the following steps:
1. HDL example design files are synthesized using XST.
2. Ngdbuild is run to consolidate the core netlist and the example design netlist into the
NGD file containing the entire design.
3. Design is mapped to the target technology.
4. Design is placed-and-routed on the target device.
5. Static timing analysis is performed on the routed design using
trce.
6. A bitstream is generated.
7. Netgen runs on the routed design to generate a VHDL or Verilog netlist (as
appropriate for the Design Entry project setting) and timing information in the form of
SDF files.
The Xilinx tool flow generates several output and report files that are saved in the
following directory (which is created by the implement script):
<project_dir>/<component_name>/implement/results
Simulation Scripts
Functional Simulation
The test script is a ModelSim, IES, or VCS macro that automates the simulation of the test
bench and is in the following location:
<project_dir>/<component_name>/simulation/functional/
The test script performs the following tasks:
• Compiles the structural UniSim simulation model
• Compiles HDL example design source code
• Compiles the demonstration test bench
• Starts a simulation of the test bench
• Opens a Wave window and adds signals of interest
• Runs the simulation to completion